Flash memory

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Flash memory is a non-volatile electronic solid-state storage device that can be electrically erased and reprogrammed.

Toshiba developed flash memory from EEPROM (readable electrically programmable read-only memory) in the early 1980s and introduced it to the market in 1984. The two main types of flash memory are named after the NAND and NOR gates. Individual flash memory cells exhibit internal characteristics similar to the corresponding gates.

While EPROM must be completely removed before rewriting, NAND type flash memory can be written and read in blocks (or pages) that are generally much smaller than the whole device. NOR-type flash allows one word machine (byte) to be written - to a deleted location - or read independently.

The NAND type operates primarily in memory cards, USB flash drives, solid-state drives (manufactured in 2009 or later), and similar products, for general storage and data transfer. NAND or NOR flash memory is also commonly used to store configuration data in various digital products, tasks previously enabled by EEPROM or battery-powered static RAM. One of the main disadvantages of flash memory is that it can only withstand a relatively small number of write cycles within a particular block.

Examples of applications of both types of flash memory include personal computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, video games, scientific instrumentation, industrial robotics, and medical electronics. In addition to non-volatile, flash memory offers fast read access time, although not as fast as static RAM or ROM. Its mechanical shock resistance helps explain its popularity over hard disks in portable devices, such as high durability, high pressure resisting capability, temperature and immersion in water, etc.

Although flash memory is technically a type of EEPROM, the term "EEPROM" is commonly used to refer specifically to a non-flash EEPROM that can be removed in small blocks, usually bytes. Due to the slow wipe cycle, the large block size used in flash memory deletion provides a significant speed advantage over non-flash EEPROM when writing large amounts of data. In 2013, the cost of flash memory is much less than programmable EEPROM and has become the dominant memory type wherever the system requires large amounts of non-volatile solid-state storage.

Video Flash memory

History

Flash memory (both NOR and NAND type) was invented by Fujio Masuoka while working for Toshiba around 1980. According to Toshiba, the name "flash" was suggested by Masuoka's colleague, Sh? Ji Ariizumi, because the process of deleting the contents of memory reminds him of the camera flash. Masuoka and colleagues presented this discovery at the IEEE 1987 International Electron Devices Meeting (IEDM) held in San Francisco.

Intel Corporation introduced the first commercial-type NOR flash chip in 1988. NOR-based flash has long write and write times, but provides full address and data bus, allowing random access to any memory location. This makes it a suitable substitute for older read-only (ROM) memory chips, which are used to store program code that rarely needs to be updated, such as a computer BIOS or set-top box firmware. Durability can be from at least 100 deletion cycles for on-chip flash memory, to the more common 10,000 or 100,000 eraser cycle, up to 1,000,000 eraser cycles. NOR-based flash is the basis of early flash-based removable media; CompactFlash was originally based on that, although the cards then moved to a cheaper NAND flash.

NAND Flash reduces deletion and write time, and requires fewer chip areas per cell, allowing greater storage density and lower cost per bit than NOR flash; it also has up to 10 times the resistance of NOR flash. However, the NAND flash I/O interface does not provide an external random-access address bus. Instead, the data should be read block-wise, with a typical block size of hundreds to thousands of bits. This makes NAND flash unsuitable as a drop-in replacement for ROM programs, as most microprocessors and microcontrollers require random access byte levels. In this case, NAND flash is similar to other secondary data storage devices, such as hard disks and optical media, and thus very suitable for use in mass storage devices, such as memory cards. The first NAND removable media format was SmartMedia in 1995, and many others followed, including:

• MultiMediaCard
• Secure Digital
• Memory Stick, and xD-Picture Card.

The new generation of memory card formats, including RS-MMC, miniSD and microSD, feature a very small form factor. For example, a microSD card has an area of ​​more than 1.5 cm ² , with a thickness of less than 1 mm. In August 2017 a microSD card with a capacity of up to 400 GB (400 billion bytes) is available.

Maps Flash memory

Principles of operation

Flash memory stores information in the memory cell array created from floating gate transistors. In a single-level cell device (SLC), each cell stores only one bit of information. The Multi-Level Cell (MLC) device, including a triple-level cell (TLC) device, can store more than one bit per cell.

Floating gates may be conductive (usually polysilicon in most types of flash memory) or non-conductive (as in SONOS flash memory).

floating gate-transistor

In flash memory, each memory cell resembles a metal-oxide-semiconductor field effect transistor (MOSFET) except that the transistor has two gates instead of one. The cells can be seen as electrical switches where currents flow between two terminals (source and drain) and controlled by a floating gate (FG) and control gate (CG). Above is the control gate (CG), as in other MOS transistors, but below, there is a floating gate (FG) that is isolated around by the oxide layer. FG is inserted between CG and MOSFET channel. Since FG is electrically isolated by its insulating layer, the electrons placed on it are trapped until they are removed by other applications of the electric field (eg the voltage or UV applied to the EPROM). In a counter-intuitive way, placing electrons in FG sets the transistors to a logical "0" state. After the FG is filled, the electrons in it (partially) cancel the electric field from the CG, thereby increasing the threshold voltage (V _T1 ) of the cell. This means that now a higher voltage (V _T2 ) should be applied to CG to create a conductive channel. To read the value of the transistor, the intermediate voltage between the threshold voltage (V _T1 & amp; V _T2 ) is applied to CG. If the channel performs at this medium voltage, the FG must be uncharged (if filled, we will not get conduction because the medium voltage is less than V _T2 ), and therefore, logical "1" is stored at the gate. If the channel does not perform at medium voltage, this indicates that the FG is charged, and hence, "0" is logically stored at the gate. The logical presence of "0" or "1" is felt by determining whether there is a current flowing through the transistor when the intermediate voltage is affirmed in CG. In multi-level cell devices, which store more than one bit per cell, the amount of perceived current flow (not just the presence or absence), to determine more precisely the degree of charge on the FG.

Fowler-Nordheim Tuning Effect

The process of moving electrons from the control gate and to the floating gate is called the Fowler-Nordheim tunnel effect, and fundamentally alters the cell characteristics by increasing the threshold voltage of the MOSFET. This, in turn, converts the current source-drain that flows through the transistor to a given gate voltage, which is ultimately used to encode the binary value. The Fowler-Nordheim tunneling effect is reversible, so electrons can be added or removed from the floating gate, a process traditionally known as writing and deletion.

Internal payload pump

Despite the need for high programming and removing voltages, almost all current flash chips require only a single supply voltage and generate high voltage using on-chip charge pumps.

More than half of the energy used by the 1.8 NAND VAND flash chip is lost in the charge of the pump itself. Because converter boosts are inherently more efficient than charge pumps, the researchers developed low-powered SSDs have proposed returning to the dual Vcc/Vpp supply voltage used on all initial flash chips, pushing high Vpp voltages for all flash chips in the SSD with one enhanced converter increase external.

In spacecraft and other high-radiation environments, on-chip charge pumps are the first part of a failed flash chip, although flash memory will continue to work - in read-only mode - at much higher radiation levels.

NOR flash

In NOR flash, each cell has one end connected directly to the ground, and the other end connects directly to the bit line. This setting is called "NOR flash" because it functions like a NOR gate: when one of the word lines (connected to the CG cell) is carried high, the corresponding storage transistor acts to draw a low output bit. NOR flash remains the preferred technology for embedded applications that require discrete non-volatile memory devices. Low read latency characters from NOR devices allow direct code execution and data storage in a single memory product.

Programming

One NOR flash cell level in its default state is logically equivalent to a binary "1" value, since the current will flow through the channel under the application of the appropriate voltage to the control gate, so that the bitline voltage is pulled down. A NOR flash cell can be programmed, or set to "0" binary value, with the following procedure:

• increase in voltage (typically & gt; 5V) applied to CG
• the channel is now turned on, so the electrons can flow from the source to the drain (assuming NMOS transistor)
• Current-channel sources are high enough to cause some high-energy electrons to jump through the insulating layer to FG, through a process called heat-injection electrons.

Delete

To remove the NOR flash cell (resets to the "1" state), the large voltage of the opposite polarity is applied between CG and the source terminals, drawing electrons from FG through the quantum tunnel. Modern NOR flash memory chips are divided into segments delete (often called blocks or sectors). Removal operations can be done only on the basis of block-wise; all cells in the deleted segment should be deleted together. NOR cell programming, however, can generally be performed one byte or word at a time.

Flash NAND

NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: some transistors are connected in series, and bit lines are pulled low only if all lines are pulled high (above transistor) V _T ). These groups are then connected through several additional transistors to the NOR-style bit line arrangement in the same way that one transistor is connected in NOR flash.

Compared with NOR flash, replacing single transistors with serial-linked groups adds extra level of addressing. Whereas NOR flash may be memory address with page then word, NAND flash may be address with page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which only accesses one bit at a time. The Execute-in-place application, on the other hand, requires every bit in a word to be accessed simultaneously. This requires addressing the word level. In any case, the addressing mode of bits and words can be done with NOR or NAND flash.

To read the data, first the desired group is selected (in the same way as one transistor is selected from the NOR array). Furthermore, most of the word lines are pulled up V _T of the programmed bit, while one of them is pulled up V _T of a deleted bit.. The series group will perform (and draw a low bit line) if the selected bit is not already programmed.

Despite the additional transistors, the reduction of ground wires and bit lines allows for more solid layout and larger storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagram.) In addition, NAND flash is usually allowed to contain a certain number of errors (NOR flash, as used for BIOS ROM, is expected to be error-free). Manufacturers try to maximize the amount of storage that can be used by shrinking the size of transistors.

Write and delete

NAND Flash uses tunnel injection for tunnel release and writing to be removed. NAND flash memory forms the core of a removable USB storage device known as a USB flash drive, as well as most of the current memory card and solid-state drive formats available.

NAND Vertic

Vertical NAND (V-NAND) memory accumulates memory cells vertically and uses the charging trap architecture. The vertical layer allows the density of larger area bits without requiring smaller individual cells.

Structure

V-NAND uses flash trap charge geometry (pioneered in 2002 by AMD) that stores the charge on an embedded silicon nitride film. Such films are stronger against point defects and can be made thicker to hold larger numbers of electrons. The V-NAND wraps the planar cargo trap cell into a cylindrical shape.

The hierarchical structure of the NAND Flash starts at the cellular level that sets the string, then the page, blocks, planes and eventually dies. A string is a series of connected NAND cells where a single cell source is connected to the next channel. Depending on NAND technology, the string typically consists of 32 to 128 NAND cells. Strings are arranged into pages that are then organized into blocks where each string is connected to a separate channel called a bitline (BL) All cells of the same position in the string are connected through the control gate by a wordline (WL) A plane containing a number of blocks connected through the same BL. Dead Flash consists of one or more planes, and the peripheral circuitry required to perform all read/write/delete operations.

Individual memory cells consist of a planar polysilicon layer containing a hole filled by several concentric vertical cylinders. The polysilicon surface of the hole acts as a gate electrode. The outer silicon dioxide cylinder acts as a dielectric gate, enclosing a silicon nitride cylinder that stores the charge, in turn enclosing a silicon dioxide cylinder as a tunnel dielectric that surrounds the central rod of conducting polysilicon acting as a conductor channel.

Memory cells in different vertical layers do not interfere with each other, as the charge can not move vertically through the silicon nitride storage medium, and the electric field associated with the gate is closely confined within each layer. Electrical vertical collection is identical to serial connected groups where conventional NAND flash memory is configured.

Construction

The growth of a group of V-NAND cells begins with a stack of layers of polysilicon conductor (doped) and an isolated silicon dioxide layer.

The next step is to form a cylindrical opening through these layers. In practice, the 128-Gibit V-NAND chip with 24 layers of memory cells requires about 2.9 billion such holes. Furthermore the inner surface of the hole receives several layers, first silicon dioxide, then silicon nitride, then a second layer of silicon dioxide. Finally, the hole is filled with a polysilicon conductor (doped).

Performance

In 2013, the V-NAND flash architecture enables read and write operations twice as fast as conventional NANDs and can last up to 10 times longer, while consuming 50 percent less power. They offer a comparable physical bits density using 10-nm lithography, but may increase the density of bits up to two-fold.

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Limitations

Block removal

One limitation of flash memory is that, although it can be read or programmed bytes or words at a time in random access mode, it can be deleted only one block at a time. This generally sets all the bits in the 1st block. Starting with the newly deleted block, every location within the block can be programmed. However, once the bit has been set to 0, simply by removing the entire block can be changed back to 1. In other words, flash memory (specifically NOR flash) offers random read access and programming operations, but does not offer arbitrarily. random access rewriting or deleting operation. A location can, however, be rewritten as long as new values ​​of 0 bits are a superset of over-written values. For example, the nibble value can be removed to 1111, then written as 1110. Successive writes to the nibble can change it to 1010, then 0010, and finally 0000. Basically, the deletion assigns all bits to 1, and programming can only clear the bits into 0. Some file systems designed for flash devices make use of this rewriting capability, such as Yaffs1, to represent sector metadata. Other flash file systems, such as YAFFS2, never use this "rewrite" capability - they do a lot of extra work to fulfill "write once rules".

Although the data structure in flash memory can not be updated in a completely public way, it allows members to be "deleted" by marking it as invalid. This technique may need to be modified for multi-level cell devices, where one memory cell holds more than one bit.

Common flash devices such as USB flash drives and memory cards only provide a block level interface, or Flash translation layer (FTL), which writes to different cells each time using the same level device. This prevents gradual writing in a block; However, it does not help the device from prematurely wiped out by intensive writing patterns.

Memory usage

Another limitation is that flash memory has a limited number of programs - delete cycles (usually written as P/E cycles). Most commercially available flash products are guaranteed to survive about 100,000 P/E cycles before wearing out to impair the integrity of storage. Micron Technology and Sun Microsystems announced the SLCÃ, NAND flash memory chip that was upgraded to 1,000,000 P/E cycles on December 17, 2008.

The number of assured cycles may only apply to block zero (as with the TSOP NAND device), or to all blocks (as in NOR). This effect is reduced in some chip firmware or file system drivers by counting the writing and dynamically remapping the blocks to spread write operations across sectors; This technique is called wear leveling. Another approach is to verify write and mapping back to the backup sector in case of write failure, a technique called bad block management (BBM). For portable consumer devices, this outdated management technique usually extends the life of flash memory beyond the life of the device itself, and some data loss is acceptable in this application. For high reliability data storage, however, it is not recommended to use flash memory which must go through a large number of programming cycles. This limitation is meaningless to 'read-only' apps like thin clients and routers, which are programmed only once or at most several times during their lifetime.

In December 2012, Taiwanese engineers from Macronix expressed their intention to announce at the IEEE International Electron Devices Meeting 2012 that they have found a way to increase the NAND flash read/write storage cycle from 10,000 to 100 million cycles using a "self-healing" process that uses flash chip with "onboard heater that can combine small groups of memory cells." Built-in thermal annealing is to replace the usual elimination cycle with a local high-temperature process that not only removes the stored charge but also fixes the voltage induced by the electrons in the chip, giving the write cycle at least 100 million. The result is to be a chip that can be erased and written over and over again, even when it should theoretically be solved. Despite promising Macronix's breakthrough for the mobile industry, however, there are no plans for commercial products to be released anytime soon.

Read interrupt

The method used to read NAND flash memory can cause nearby cells in the same memory block to change over time (be programmed). This is known as a reading disorder. The number of reading thresholds is generally in the hundreds of thousands of readings between the intervention eraser operations. If it reads continuously from one cell, it will not fail but one of the surrounding cells in the next reading. To avoid trouble reading problems, the flash controller will usually count the total number of readings to the block since the last deletion. When the count exceeds the target limit, the affected blocks will be copied to the new block, deleted, then released to the block. Original blocks are as good as new ones after deletion. If the flash controller does not intervene in time, the read interrupt error will occur with the possibility of data loss if the error is too much to correct with the error correction code.

X-ray Effects

Most flash ICs come in ball grid array (BGA) packages, and even those that are not often installed on PCBs next to other BGA packages. After PCB Assembly, the board with the BGA package is often X-rayed to see if the ball makes the right connection to the right pad, or if the BGA needs to be reworked. This X-ray can erase programmed bits in a flash chip (changing the bit of program "0" to deleted "1" bit). The deleted bit ("1" bit) is not affected by X-rays.

Some manufacturers now make SD and USB devices X-ray proof memory.

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Low-level access

The low-level interface to the flash memory chip differs from other types of memory such as DRAM, ROM, and EEPROM, which support bit-alterability (both zero to one and one to zero) and random access via an externally accessible address bus.

NOR memory has external address bus for reading and programming. For NOR memory, read and programming is random access, and unlock and delete is block-wise. For NAND memory, reading and programming is page-wise, and opening and deleting is block-wise.

Memories of NOR

Reading from NOR flash is similar to reading from random access memory, as long as the address and data bus are mapped correctly. Therefore, most microprocessors can use NOR flash memory as an on-site execution memory (XIP), which means that programs stored in NOR flash can be run directly from NOR flash without the need to be copied to RAM first. NOR flash may be programmed by means of random access that is similar to reading. Programming changes bits from logical to zero. The zero bit is left unchanged. Deletion must occur block at a time, and reset all bits in the deleted block back to one. Typical block size is 64, 128, or 256Ã, KiB.

Bad block management is a relatively new feature in NOR chips. On older NOR devices that do not support bad block management, software or device drivers that control the memory chip must be correct for block wear, or the device will stop functioning reliably.

Specific instructions used to lock, unlock, program, or delete different NOR memory for each manufacturer. To avoid the need for unique driver software for each device created, the Flash Memory Interface (CFI) special commands allow the device to identify itself and important operating parameters.

In addition to being used as a random access ROM, NOR flash can also be used as a storage device, by utilizing random-access programming. Some devices offer read-while-write functionality so the code continues to run even when program or removal operations occur in the background. To write sequential data, NOR flash chips usually have slow write speeds, compared to NAND flash.

Typical NOR flash does not require error correction code.

NAND Memory

The NAND flash architecture was introduced by Toshiba in 1989. These memories are accessed like block devices, such as hard disks. Each block consists of a number of pages. Pages typically are 512 or 2,048 or 4,096 bytes. Associated with each page is a few bytes (usually 1/32 of the data size) that can be used for storing checksum error correction code (ECC).

Common block sizes include:

• 32 pages of 512 16 bytes each for block size (effective) of 16 KB
• 64 pages 2,048 64 bytes each for block size 128Ã, KB
• 64 pages 4,096 128 bytes each for block size 256Ã, KB
• 128 pages of 4,096 128 bytes each for block size 512Ã, KB.

When reading and programming is done on a page base, deletion can only be done by block.

NAND devices also require bad block management by device driver software, or by a separate controller chip. SD cards, for example, include control circuits to perform bad block management and leveling wear. When a logical block is accessed by high level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip can be set aside for storing mapping tables to handle bad blocks, or the system can only check every block in power-up to make bad block maps in RAM. The overall memory capacity gradually shrinks as more blocks are marked as bad.

NAND relies on ECC to offset bits that may spontaneously fail during normal device operation. A typical ECC will fix a one-bit error in every 2048 bit (256 bytes) using 22 bit ECC, or a one-bit error in every 4096 bit (512 bytes) using 24 bit ECC. If ECC can not fix errors while reading, it may still detect errors. When performing a removal operation or program, the device can detect blocks that failed to program or delete and mark it as bad. The data is then written to a different block, either, and the bad block map is updated.

Hamming codes are the most commonly used ECC for flash SLCÃ, NAND. Reed-Solomon codes and Bose-Chaudhuri-Hocquenghem codes are commonly used ECC for flash MLCÃ, NAND. Some internal MLC NAND flash chips produce correct BCH error correction codes.

Most NAND devices are shipped from the factory with some bad blocks. This is usually marked according to the strategy of marking the bad block specified. By allowing some bad blocks, manufacturers achieve much higher results than is possible if all blocks must be verified properly. This significantly reduces the cost of NAND flash and only slightly decreases the storage capacity of its parts.

When executing software from NAND memory, virtual memory strategies are often used: the memory content must be first paged or copied to memory-mapped RAM and run there (leading to a common combination of NAND RAM). The memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlay. For this reason, some systems will use a combination of NOR and NAND memory, where smaller NOR memory is used as software ROM and larger NAND memory is partitioned with a file system for use as a non-volatile data storage area.

NAND sacrifices the advantages of random access and on-site execution of NOR. NAND is best suited for systems that require high-capacity data storage. It offers higher density, greater capacity, and lower cost. It has faster erase, sequential writing, and sequential reading.

Standardization

A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standard low-level interface for NAND flash chips. This allows interoperability between tailoring NAND devices from different vendors. The ONFI specification version 1.0 was released on December 28, 2006. It establishes:

• standard physical interface (pinout) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages
• standard command to read, write, and delete NAND flash chips
• a mechanism for self-identification (compared to the serial attendance detection feature of the SDRAM memory module)

The ONFI group is supported by major NAND flash manufacturers, including Hynix, Intel, Micron Technology, and Numonyx, as well as by major manufacturers of devices that incorporate NAND flash chips.

Two major flash device manufacturers, Toshiba and Samsung, have chosen to use their own design interface known as Toggle Mode (and now Toggle V2.0). This interface does not match pin-to-pin with the ONFI specification. The result is a product designed for one vendor device may not be able to use another vendor's device.

A group of vendors, including Intel, Dell, and Microsoft, formed the Non-Volatile Memory Host Control Working Group (NVMHCI). The purpose of this group is to provide standard software and hardware programming interfaces for non-volatile memory subsystems, including "flash cache" devices connected to PCI Express buses.

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Difference between NOR and NAND flash

NOR and NAND flash differ in two important ways:

• connections from each memory cell are different
• the interface provided for reading and writing different memory (NOR allows random access to read, NAND only allows page access)

Both are linked by design choices made in the development of NAND flash. The purpose of NAND flash development is to reduce the chip area required to implement the capacity of the given flash memory, and thus reduce the cost per bit and increase the maximum chip capacity so that flash memory can compete with magnetic storage devices such as hard disks.

NOR and NAND flash get their name from the interconnect structure between the memory cells. In NOR flash, cells connect in parallel with the bit line, allowing the cells to be read and programmed individually. The parallel cell connection resembles the parallel connection of the transistor at the NOS CMOS gate. In NAND flash, cells are connected in series, resembling a NAND CMOS gate. Connection series consumes less space than parallel, reducing the cost of NAND flash. It does not, by itself, prevent NAND cells from being read and programmed individually.

Each NOR flash cell is bigger than a NAND flash cell - 10 F ² vs 4 F ² - even when using the same semiconductor device fabrication and every transistor, contact, which is exactly the same - because NOR flash cells require separate metal contacts for each cell.

When NOR flash is developed, it is conceivable as rewritable ROM is more economical and convenient than contemporary EPROM and EEPROM memories. Thus, a random access reading circuit is required. However, it is expected that the NOR flash ROM will be more readable than written, so the writing sequence includes quite slow and can only be removed in a wise manner. On the other hand, applications that use flash instead of disk drives do not require a word-level write address, which will only add unnecessary complexity and cost.

Due to serial connections and deletion of wordline contacts, a large box of NAND flash memory cells will occupy perhaps only 60% of the equivalent NOR cell area (assuming the same CMOS process resolution, for example, 130 nm, 90 nm, or 65 nm). Designer NANDÃ, flash realizes that the NAND chip area, and thus cost, can be further reduced by removing external addresses and data bus circuits. In contrast, external devices can communicate with NAND flash through commands and registers of sequentially accessed data, which internally retrieve and extract the required data. This design option makes random access to NAND flash memory impossible, but the purpose of NAND flash is to replace the hard disk mechanically, not to replace ROM.

Write endurance

The write-through power of the NOR flash floating-gang SLC is usually the same as or greater than the NAND flash, while the NOR and NAND MLC flash have the same endurance capabilities. Examples of durability cycle ratings listed in the data sheets for NAND and NOR flash, as well as on storage devices using flash memory, are provided.

However, by applying certain design algorithms and paradigms such as wear leveling and memory over-provisioning, storage system resilience can be set to serve certain requirements.

To calculate the longevity of a NAND flash, one must take into account the size of the memory chip, the type of memory (eg SLC/MLC/TLC), and usage patterns.

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Flash file system

Due to the special characteristics of flash memory, it is best used with a controller to perform wear and error correction or specially designed flash file system, which spreads writing over the media and is related to the long delete time of the NOR flash. The basic concept behind the flash file system is as follows: when the flash store will be updated, the file system will write a new copy of the converted data to the new block, re-map the file pointer, then delete the old block later when it has time.

In practice, the flash file system is only used for memory technology (MTD) devices, which are embedded flash memory that has no controllers. Removable flash memory cards and USB flash drives have built-in controllers for wear and error correction so that the use of certain flash file systems does not add to any benefits.

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Capacity

Some chips are often in-array to achieve higher capacity for use in consumer electronic devices such as multimedia or GPS players. The capacity of flash chips generally follows Moore's Law because they are manufactured with many of the same integrated circuit techniques and equipment.

The customer flash storage device is usually advertised with a usable size expressed as a small integer of two (2, 4, 8, etc.) and the designation of megabytes (MB) or gigabytes (GB); for example, 512 MB, 8 GB. These include SSDs that are marketed as hard drive replacements, according to traditional hard drives, which use decimal prefixes. Thus, SSDs marked as "64 GB" are at least 64 ÃÆ'â € "1000 ³ bytes (64Ã, GB). Most users will have less capacity than is available for their files, since space is taken up by system file metadata.

The flash memory chip inside is sized in a tight binary multiplier, but the total chip capacity is not actually usable on the drive interface. This is much larger than the advertised capacity to allow writing distribution (leveling), to save, for error correction codes, and for other metadata required by the device's internal firmware.

In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using multi-level cell (MLC) technology, capable of storing two data bits per cell. In September 2005, Samsung Electronics announced that it has developed the first 2 GB chip in the world.

In March 2006, Samsung announced a flash drive with a capacity of 4 GB, essentially the same order of magnitude as a smaller laptop hard drive, and in September 2006, Samsung announced an 8 GB chip manufactured using a 40nm manufacturing process. In January 2008, SanDisk announced the availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.

The newer flash drive (in 2012) has a much larger capacity, has 64, 128, and 256 GB.

The joint development at Intel and Micron will enable the production of 32-layer 3.5 terabytes (TB) of NAND flash stick and 10-TB SSD of standard size. This device includes 5 packages of 16 ÃÆ'â € "48Ã, GB TLC dies, using a floating gate cell design.

The Flash chip continues to be produced with capacity below or about 1 MB, for example, for BIOS-ROM and embedded applications.

In July 2016, Samsung announced the Samsung 4TB 850 EVO utilizing a 256 Gb 48-layer TLC 3D V-NAND. In August 2016, Samsung announced 2.5-inch SAS 2.5-inch SAS based on the 512 Gb 64-layer TLC 3DÃ, V-NAND. Furthermore, Samsung expects to unveil SSDs with up to 100 TB of storage by 2020.

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Transfer rate

Flash memory devices are usually faster in reading than writing. Performance also depends on the quality of storage controllers becoming more important when the device is partly full. Even when the only change in manufacturing is dead-shrinking, the absence of the right controller can produce a degraded velocity.

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Apps

Serial flash

Serial flash is a small, low power flash that provides only serial access to data - rather than individual byte handles, the user reads or writes a group of large adjacent bytes in the address space in series. Serial Peripheral Interface Bus (SPI) is a common protocol for accessing devices. When inserted into an embedded system, serial flash requires less cable on the PCB than parallel flash memory, therefore transmits and receives data bit by bit. This can allow reduction of board space, power consumption, and total system cost.

There are several reasons why serial devices, with fewer external pins than parallel devices, can significantly reduce overall costs:

• Many ASICs are limited pad, meaning that the size of the dice is limited by the number of binding wire pads, rather than the complexity and number of gates used for the logic of the device. Eliminates the bonding pads so as to allow a more compact integrated circuit, on smaller dies; this increases the amount of die that may be made on the wafer, and thus reduces the cost per die.
• Reducing the number of external pins also reduces assembly and packaging costs. Serial devices can be packaged in smaller and simpler packages than parallel devices.
• Smaller and lower pin-count packets occupy less PCB areas.
• The lower pin-count device simplifies PCB routing.

There are two main flash SPI types. The first type is marked with a small page and one or more internal SRAM page buffers that allow the complete page to be read into a buffer, partially modified, and then rewritten (for example, Atmel AT45 DataFlash or Micron Technology Page Deletes NOR Flash ). The second type has a larger sector. The smallest sector usually found in SPI flash is 4 kB, but they can be 64 kB. Since flash SPI does not have an internal SRAM buffer, the full page should be read and modified before rewriting, making it slow to manage. SPI flash is cheaper than DataFlash and is therefore a good choice when apps shadow the code.

Both types are not easy to exchange, because they do not have the same pinout, and the command set is not compatible.

Most FPGAs are based on SRAM configuration cells and require external configuration devices, often serial flash chips, to reload the bitstream configuration of each power cycle.

Firmware storage

With the increasing speed of modern CPUs, parallel flash devices are often much slower than the computer memory buses connected to them. In contrast, modern SRAMs offer access times in under 10 seconds, while DDR2 SDRAM offers access times in under 20 seconds. Because of this, often desired shadow codes are stored in flash to RAM; ie, the code is copied from flash to RAM before execution, so the CPU can access it at full speed. Device firmware can be stored in serial flash devices, and then copied to SDRAM or SRAM when the device is turned on. Using external serial flash devices rather than on-chip flash eliminates the need for a significant compromise process (a good process for high-speed logic is generally not good for flash and vice versa). Once it is decided to read the firmware as one big block, we usually add compression to allow smaller flash chips to use. Common applications for serial flash include storing firmware for hard drives, Ethernet controllers, DSL modems, wireless network devices, etc.

Flash memory instead of hard drive

One more recent application for flash memory is as a replacement hard disk. Flash memory has no mechanical limitations and hard drive latency, so the solid-state drive (SSD) is attractive when considering speed, noise, power consumption, and reliability. Flash drives gain attraction as a secondary mobile device storage device; they are also used in place of hard drives on high-performance desktop computers and some servers with RAID and SAN architectures.

There are still some aspects of flash-based SSD that make them unattractive. The cost per gigabyte of flash memory remains much higher than the hard disk. Flash memory also has a limited number of P/E cycles, but this seems currently under control because of the warranty on flash-based SSDs approaching the current hard drive. Additionally, files deleted on SSDs can remain unlimited before being overwritten by new data; removal or damaged techniques or software that works well on magnetic hard disk drives has no effect on SSDs, sacrificing security and forensic examinations.

For relational databases or other systems that require ACID transactions, even the amount of simple flash storage can offer great acceleration through disk drive arrays.

In June 2006, Samsung Electronics released the first flash-memory-based PC, Q1-SSD and Q30-SSD, both using 32 GB SSD, and at least initially only available in South Korea.

The solid-state hard disk is offered as an option with the first MacBook Air introduced in 2008, and from 2010 onwards, all models are shipped with SSDs. Beginning in late 2011, as part of the Intel Ultrabook initiative, more and more ultra-thin laptops are delivered with SSD standards.

There are also hybrid techniques like hybrid drives and ReadyBoost that try to combine the advantages of both technologies, using flash as a high-speed non-volatile cache for files on frequently referenced disks, but rarely modified, such as executable file and executable file applications.

Flash memory as RAM

In 2012, there is an attempt to use flash memory as the main computer memory, DRAM.

Archive storage or long term

It is unclear how long flash memory will last under archival conditions - that is, benign temperatures and moisture with rare access with or without prophylactic writing. Anecdotal evidence suggests that this technology is strong enough on a year-scale. The datasheet of the Atmel flash-based ATmega microcontroller generally promises a 20-year retention time at 85 ° C (185 ° F) and 100 years at 25 ° C (77 ° F).

An article from CMU in 2015 writes that "Today's flash devices, which do not require flash refresh, have a typical 1-year retention age at room temperature." And that temperature can decrease retention time exponentially. This phenomenon can be modeled by Arrhenius law.

FPGA Configuration

Some FPGAs are based on flash configuration cells that are used directly as (programmed) switches to connect internal elements together, using a kind of floating-gate transistor as a flash data storage cell on a data storage device.

src: cdn.instructables.com

Industry

One source states that, in 2008, the flash memory industry included about US $ 9.1 billion in production and sales. Another source puts the flash memory market at a size of over US $ 20 billion in 2006, accounting for more than eight percent of the semiconductor market as a whole and more than 34 percent of the total semiconductor memory market. In 2012, the market is expected to reach $ 26.8 billion.

src: www.bhphotovideo.com

Flash scalability

Due to its relatively simple structure and high demand for higher capacity, NAND flash memory is the most aggressive scale technology among electronic devices. The heavy competition among some top manufacturers only adds aggressiveness in shrinking design rules or process technology nodes. While the expected depreciation timeline is a factor of two every three years per original version of Moore's law, it has recently accelerated in case of NAND flash to a factor of two every two years.

Because the size of the flash memory cell feature reaches the minimum 15-16 nm, further flash density increases will be driven by TLC (3 bits/cell) combined with the vertical arrangement of NAND memory fields. Decrease in endurance and increase the non-corrected bit error rate that accompanies feature feature depreciation can be compensated with an improved error correction mechanism. Even with these advances, it may not be possible to flash economies of scale to smaller and smaller dimensions as the number of electron retention capacities decreases. Many promising new technologies (such as FeRAM, MRAM, PMC, PCM, ReRAM, etc.) are being investigated and developed as the possibility of more scalable replacement for flash.

src: www.flashbay.com

See also

• List of flash file systems
• microSDXC (up to 2 TB)
• Secure USB drive
• Open the NAND Flash Interface Work Group
• Write amplification
• NAND Gate
• NOR Gate

src: thumbs.dreamstime.com

References

src: www.promokeychain.com

External links

• Semiconductor Characterization System has various functions
• NAND Flash Applications Design Guide by Toshiba, April 2003 v. 1.0
• Understand and select a high performance NAND architecture
• How flash storage works by a presentation by David Woodhouse from Intel
• Flash endurance test
• http://www.spansion.com/Support/Application Notes/EnduranceRetention_AN.pdf
• http://www.cse.scu.edu/~tschwarz/coen180/LN/flash.html
• NAND Flash Data Recovery Cookbook
• Flash Memory Types by OpenWrt

Source of the article : Wikipedia